Efficient First Order Sigma Delta Modulators

In communication systems the present trend is to move the border between the analog and digital interface as close as possible to the point where information is received or emitted, in this way most of SoC functionalities are implemented in the digital domain. in this work an efficient first order sigma delta modulator has been designed in circuit level, considering the possible non-idealities in 65nm CMOS technology .this study at first determines the of sigma delta modulator. The non idealities investigated here are clock jitter noise that affects the input signal and increases total error power; then the thermal noise of switches caused by random fluctuation of carrier that increases the total noise power thereafter, circuit leakage causes the limited DC gain and affects signal to noise ratio sum distortion ratio. The non idealities are reduced by using folded cascade op-amp at the integrator stage designed using Pspice simulation tool which can be implemented for practical usage. INTRODUCTION The sigma delta modulator was first discovered in 1960’s but due to the technological limitation its implementation is difficult but now a days the VLSI technology is so much improved so it can be implemented easily, it is happening also the sigma delta modulator are being used I the mobile communication (wireless and wire line communication), sensors, digital signal processors, audio processors, etc. The block diagram of a sigma delta modulator is situated below in Fig. 1, this diagram consists of three parts, first is anti-aliasing filter which is responsible for the non overlapping of the signal, second one is the main part which is called the sigma delta modulator which described under same topic later. The third part is decimator which is consists of a digital filter and a down sampler. In the sigma delta modulator, the Greek letter-∆ (delta) is used to show the deviation or small increment change, the process came to know as “delta modulation”. Delta modulation is based on quantizing the change in the signal from sample to sample rather than the absolute value of the signal at each sample. Sigma stands for summing or integrating, which is performed at the input stage on the digital output with the input signal before the delta modulation. Hence the analog to digital conversion of this technique called sigma delta modulation. International Journal of Advanced Engineering Technology E-ISSN 0976-3945 IJAET/Vol.I/ Issue II/July-Sept.,2010/99-105 Fig 1 block diagram of sigma delta adc The 1 st order sigma-delta modulator design consist of mainly an integrator, a comparator and a D/A converter the single-bit feedback D/A converter (DAC) output is subtracted from the analog input signal in the summing amplifier. As shown in Fig. 2. The resultant error signal from the summing amplifier output is low pass filtered by the integrator and the integrated error signal polarity is detected by the single comparator. This comparator is effectively a 1-bit A/D converter (ADC) this architecture achieves a wide range of resolution and a higher bandwidth. Settling time is an important parameter which determines the resolution of an ADC. It is defined as a small amount of time required for an ADC to reach certain accuracy. If the settling time is linearly dependent on the input signal, a high resolution performance can be achieved even if the integrator does not settle to the full resolution to the converter. Fig 2: block diagram of a 1 st order sigma delta modulator International Journal of Advanced Engineering Technology E-ISSN 0976-3945 IJAET/Vol.I/ Issue II/July-Sept.,2010/99-105 In this paper, the non-idealities of sigma delta modulator have been investigated first and then a first order sigma delta modulator is designed using 65 nm CMOS technology. The modulator uses folded cascade op-amp to design integrator and comparator at an operating power supply of ±2.5 V. The final circuit is constructed using PSPICE simulation tools. INVESTIGATION OF THE NON-